Reference-less frequency detector with high jitter tolerance

An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit co...

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Bibliographische Detailangaben
Hauptverfasser: Deshpande, Mamatha, Gu, Liang, Lee, Hungyi, Dang, Yen, Gu, Yifan, Shih, Shou-Po, Duan, Yan, Cao, Yuming, Lei, Gong
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.