Clutter rejecting built in test for assignment-based AESA systems

Clutter rejecting built in test for assignment-based AESA systems

Methods and apparatus to provide clutter rejecting built-in-test and/or fault isolation of individual array elements in assignment-based AESAs. BIT beam states for array element testing can be stored in AESA memory for rapid assignment sequencing of RF waveform generators and receive processing. Sim...

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Hauptverfasser: Tang, David W, Lahti, David O, Stephan, Larisa Angelique Natalya
Format: Patent
Sprache:eng
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ANTENNAS, i.e. RADIO AERIALS
BASIC ELECTRIC ELEMENTS
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION
WIRELESS COMMUNICATIONS NETWORKS
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creator Tang, David W
Lahti, David O
Stephan, Larisa Angelique Natalya
description Methods and apparatus to provide clutter rejecting built-in-test and/or fault isolation of individual array elements in assignment-based AESAs. BIT beam states for array element testing can be stored in AESA memory for rapid assignment sequencing of RF waveform generators and receive processing. Simultaneously transmitted signals for BIT sequences have unique signal characteristics that allow test signal clutter rejection on the receive side processing.
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subjects ANTENNAS, i.e. RADIO AERIALS
BASIC ELECTRIC ELEMENTS
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION
WIRELESS COMMUNICATIONS NETWORKS
title Clutter rejecting built in test for assignment-based AESA systems
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