Resistive memory architectures with multiple memory cells per access device
A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive me...
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| creator | Liu, Jun Violette, Michael P |
| description | A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10424729B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10424729B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10424729B23</originalsourceid><addsrcrecordid>eNqNyj0KAjEQBtA0FqLeYTyAoHFBbBVFsPOnXsL4LTuQuCEzu-LtbcTa6jVv7M4XqKjJAEpIXXlTKNyKga0vUHqJtZT6aJLjrzBiVMooFJihSg8Mwpi6UROiYvZ14ubHw21_WiB3NTQHxhNW36-rZeWrjd_u_Pqf8wHJnzZK</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Resistive memory architectures with multiple memory cells per access device</title><source>esp@cenet</source><creator>Liu, Jun ; Violette, Michael P</creator><creatorcontrib>Liu, Jun ; Violette, Michael P</creatorcontrib><description>A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190924&DB=EPODOC&CC=US&NR=10424729B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190924&DB=EPODOC&CC=US&NR=10424729B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Liu, Jun</creatorcontrib><creatorcontrib>Violette, Michael P</creatorcontrib><title>Resistive memory architectures with multiple memory cells per access device</title><description>A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyj0KAjEQBtA0FqLeYTyAoHFBbBVFsPOnXsL4LTuQuCEzu-LtbcTa6jVv7M4XqKjJAEpIXXlTKNyKga0vUHqJtZT6aJLjrzBiVMooFJihSg8Mwpi6UROiYvZ14ubHw21_WiB3NTQHxhNW36-rZeWrjd_u_Pqf8wHJnzZK</recordid><startdate>20190924</startdate><enddate>20190924</enddate><creator>Liu, Jun</creator><creator>Violette, Michael P</creator><scope>EVB</scope></search><sort><creationdate>20190924</creationdate><title>Resistive memory architectures with multiple memory cells per access device</title><author>Liu, Jun ; Violette, Michael P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10424729B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Liu, Jun</creatorcontrib><creatorcontrib>Violette, Michael P</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Liu, Jun</au><au>Violette, Michael P</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Resistive memory architectures with multiple memory cells per access device</title><date>2019-09-24</date><risdate>2019</risdate><abstract>A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Resistive memory architectures with multiple memory cells per access device |
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