Image sensor including first and second overlapping device isolation patterns

An image sensor includes a lower substrate including logic circuits and an upper substrate including pixels. Transistors provided on the upper substrate have the same conductivity type. Each of the transistors includes source/drain regions provided in the upper substrate, an upper gate electrode pro...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
1. Verfasser:	Ihara, Hisanori
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	Ihara, Hisanori
description	An image sensor includes a lower substrate including logic circuits and an upper substrate including pixels. Transistors provided on the upper substrate have the same conductivity type. Each of the transistors includes source/drain regions provided in the upper substrate, an upper gate electrode provided on the upper substrate, and a silicon oxide layer disposed between the upper substrate and the upper gate electrode. The silicon oxide layer is in physical contact with the upper substrate and the upper gate electrode.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10424611B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10424611B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10424611B23</originalsourceid><addsrcrecordid>eNqNyjEOwjAMQNEsDAi4gzkAEikVBwCBYGAC5spK3MpSsKM49PwUiQMw_eH9ubtdXzgQGIlpAZaQ3pFlgJ6LVUCJEwWdoiOVhDl_MdLIgYBNE1ZWgYy1UhFbulmPyWj168Ktz6fH8bKhrB1ZxkBCtXve_bZt2r33h2b3z_MBF0022Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Image sensor including first and second overlapping device isolation patterns</title><source>esp@cenet</source><creator>Ihara, Hisanori</creator><creatorcontrib>Ihara, Hisanori</creatorcontrib><description>An image sensor includes a lower substrate including logic circuits and an upper substrate including pixels. Transistors provided on the upper substrate have the same conductivity type. Each of the transistors includes source/drain regions provided in the upper substrate, an upper gate electrode provided on the upper substrate, and a silicon oxide layer disposed between the upper substrate and the upper gate electrode. The silicon oxide layer is in physical contact with the upper substrate and the upper gate electrode.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190924&DB=EPODOC&CC=US&NR=10424611B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190924&DB=EPODOC&CC=US&NR=10424611B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ihara, Hisanori</creatorcontrib><title>Image sensor including first and second overlapping device isolation patterns</title><description>An image sensor includes a lower substrate including logic circuits and an upper substrate including pixels. Transistors provided on the upper substrate have the same conductivity type. Each of the transistors includes source/drain regions provided in the upper substrate, an upper gate electrode provided on the upper substrate, and a silicon oxide layer disposed between the upper substrate and the upper gate electrode. The silicon oxide layer is in physical contact with the upper substrate and the upper gate electrode.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEOwjAMQNEsDAi4gzkAEikVBwCBYGAC5spK3MpSsKM49PwUiQMw_eH9ubtdXzgQGIlpAZaQ3pFlgJ6LVUCJEwWdoiOVhDl_MdLIgYBNE1ZWgYy1UhFbulmPyWj168Ktz6fH8bKhrB1ZxkBCtXve_bZt2r33h2b3z_MBF0022Q</recordid><startdate>20190924</startdate><enddate>20190924</enddate><creator>Ihara, Hisanori</creator><scope>EVB</scope></search><sort><creationdate>20190924</creationdate><title>Image sensor including first and second overlapping device isolation patterns</title><author>Ihara, Hisanori</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10424611B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Ihara, Hisanori</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ihara, Hisanori</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Image sensor including first and second overlapping device isolation patterns</title><date>2019-09-24</date><risdate>2019</risdate><abstract>An image sensor includes a lower substrate including logic circuits and an upper substrate including pixels. Transistors provided on the upper substrate have the same conductivity type. Each of the transistors includes source/drain regions provided in the upper substrate, an upper gate electrode provided on the upper substrate, and a silicon oxide layer disposed between the upper substrate and the upper gate electrode. The silicon oxide layer is in physical contact with the upper substrate and the upper gate electrode.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US10424611B2
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	Image sensor including first and second overlapping device isolation patterns
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T14%3A24%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ihara,%20Hisanori&rft.date=2019-09-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10424611B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true