Partial cache coherence

Partial cache coherence

Examples disclosed herein relate to partial cache coherence. In some examples disclosed herein, a node connected to a memory fabric may include local cache connected to a local processor and a memory coherency proxy to. The memory coherency proxy may configure a portion of a fabric memory on the mem...

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Hauptverfasser: Tourrilhes, Jean, Schlansker, Michael
Format: Patent
Sprache:eng
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CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Tourrilhes, Jean
Schlansker, Michael
description Examples disclosed herein relate to partial cache coherence. In some examples disclosed herein, a node connected to a memory fabric may include local cache connected to a local processor and a memory coherency proxy to. The memory coherency proxy may configure a portion of a fabric memory on the memory fabric as a proxy backing memory and expose the proxy backing memory to other nodes in the memory fabric as a fictitious local memory on the node, and may implement partial coherency for memory requests directed to the fictitious local memory. The fictitious local memory may have a memory address region different from a memory address region of a native local memory on the node.
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In some examples disclosed herein, a node connected to a memory fabric may include local cache connected to a local processor and a memory coherency proxy to. The memory coherency proxy may configure a portion of a fabric memory on the memory fabric as a proxy backing memory and expose the proxy backing memory to other nodes in the memory fabric as a fictitious local memory on the node, and may implement partial coherency for memory requests directed to the fictitious local memory. The fictitious local memory may have a memory address region different from a memory address region of a native local memory on the node.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Partial cache coherence
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