Fabrication method of electronic package

Fabrication method of electronic package

A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the...

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Hauptverfasser: Chen, Yan-Heng, Lin, Chun-Tang, Chan, Mu-Hsuan, Chi, Chieh-Yuan
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Chen, Yan-Heng
Lin, Chun-Tang
Chan, Mu-Hsuan
Chi, Chieh-Yuan
description A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10403567B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10403567B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10403567B23</originalsourceid><addsrcrecordid>eNrjZNBwS0wqykxOLMnMz1PITS3JyE9RyE9TSM1JTS4pys_LTFYoSEzOTkxP5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcVAVal5qSXxocGGBiYGxqZm5k5GxsSoAQDPFChj</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Fabrication method of electronic package</title><source>esp@cenet</source><creator>Chen, Yan-Heng ; Lin, Chun-Tang ; Chan, Mu-Hsuan ; Chi, Chieh-Yuan</creator><creatorcontrib>Chen, Yan-Heng ; Lin, Chun-Tang ; Chan, Mu-Hsuan ; Chi, Chieh-Yuan</creatorcontrib><description>A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190903&amp;DB=EPODOC&amp;CC=US&amp;NR=10403567B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190903&amp;DB=EPODOC&amp;CC=US&amp;NR=10403567B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chen, Yan-Heng</creatorcontrib><creatorcontrib>Lin, Chun-Tang</creatorcontrib><creatorcontrib>Chan, Mu-Hsuan</creatorcontrib><creatorcontrib>Chi, Chieh-Yuan</creatorcontrib><title>Fabrication method of electronic package</title><description>A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBwS0wqykxOLMnMz1PITS3JyE9RyE9TSM1JTS4pys_LTFYoSEzOTkxP5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcVAVal5qSXxocGGBiYGxqZm5k5GxsSoAQDPFChj</recordid><startdate>20190903</startdate><enddate>20190903</enddate><creator>Chen, Yan-Heng</creator><creator>Lin, Chun-Tang</creator><creator>Chan, Mu-Hsuan</creator><creator>Chi, Chieh-Yuan</creator><scope>EVB</scope></search><sort><creationdate>20190903</creationdate><title>Fabrication method of electronic package</title><author>Chen, Yan-Heng ; Lin, Chun-Tang ; Chan, Mu-Hsuan ; Chi, Chieh-Yuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10403567B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Chen, Yan-Heng</creatorcontrib><creatorcontrib>Lin, Chun-Tang</creatorcontrib><creatorcontrib>Chan, Mu-Hsuan</creatorcontrib><creatorcontrib>Chi, Chieh-Yuan</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chen, Yan-Heng</au><au>Lin, Chun-Tang</au><au>Chan, Mu-Hsuan</au><au>Chi, Chieh-Yuan</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Fabrication method of electronic package</title><date>2019-09-03</date><risdate>2019</risdate><abstract>A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Fabrication method of electronic package
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T14%3A32%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chen,%20Yan-Heng&rft.date=2019-09-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10403567B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true