Field-effect transistor placement optimization for improved leaf cell routability

A processor-implemented method for automatically generating a layout of a cell of a semiconductor circuit is provided herein. The processor-implemented method includes reading a netlist of the cell. The netlist includes a description of internal electrical nets connecting electrical components of th...

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Bibliographische Detailangaben

Hauptverfasser:	Leefken, Iris Maria, Werner, Tobias T, Penth, Silke, Stetter, Michael
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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