Data processing system to implement wiring/silicon blockages via parameterized cells

A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEO...

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Hauptverfasser:	Malgioglio, Frank, Jatkowski, Adam R, Nett, Ryan M, Strevig, III, Gerald L, Berry, Christopher J, Palumbo, Joseph J, Salisbury, Sean
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	Malgioglio, Frank Jatkowski, Adam R Nett, Ryan M Strevig, III, Gerald L Berry, Christopher J Palumbo, Joseph J Salisbury, Sean
description	A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Data processing system to implement wiring/silicon blockages via parameterized cells
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