High performance logical device

A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating glob...

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Hauptverfasser: Cartmell, Jerome, LeCrone, Douglas E, Scharland, Michael J, McClure, Steven T
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creator Cartmell, Jerome
LeCrone, Douglas E
Scharland, Michael J
McClure, Steven T
description A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10372345B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10372345B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10372345B13</originalsourceid><addsrcrecordid>eNrjZJD3yEzPUChILUrLL8pNzEtOVcjJT89MTsxRSEkty0xO5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgbG5kbGJqZOhsbEqAEAHuck5w</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>High performance logical device</title><source>esp@cenet</source><creator>Cartmell, Jerome ; LeCrone, Douglas E ; Scharland, Michael J ; McClure, Steven T</creator><creatorcontrib>Cartmell, Jerome ; LeCrone, Douglas E ; Scharland, Michael J ; McClure, Steven T</creatorcontrib><description>A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190806&amp;DB=EPODOC&amp;CC=US&amp;NR=10372345B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190806&amp;DB=EPODOC&amp;CC=US&amp;NR=10372345B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Cartmell, Jerome</creatorcontrib><creatorcontrib>LeCrone, Douglas E</creatorcontrib><creatorcontrib>Scharland, Michael J</creatorcontrib><creatorcontrib>McClure, Steven T</creatorcontrib><title>High performance logical device</title><description>A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJD3yEzPUChILUrLL8pNzEtOVcjJT89MTsxRSEkty0xO5WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgbG5kbGJqZOhsbEqAEAHuck5w</recordid><startdate>20190806</startdate><enddate>20190806</enddate><creator>Cartmell, Jerome</creator><creator>LeCrone, Douglas E</creator><creator>Scharland, Michael J</creator><creator>McClure, Steven T</creator><scope>EVB</scope></search><sort><creationdate>20190806</creationdate><title>High performance logical device</title><author>Cartmell, Jerome ; LeCrone, Douglas E ; Scharland, Michael J ; McClure, Steven T</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10372345B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Cartmell, Jerome</creatorcontrib><creatorcontrib>LeCrone, Douglas E</creatorcontrib><creatorcontrib>Scharland, Michael J</creatorcontrib><creatorcontrib>McClure, Steven T</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cartmell, Jerome</au><au>LeCrone, Douglas E</au><au>Scharland, Michael J</au><au>McClure, Steven T</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>High performance logical device</title><date>2019-08-06</date><risdate>2019</risdate><abstract>A high performance logical device having low latency may be provided. I/Os to the logical device may be sent only to a primary director having sole ownership of the logical device. The primary director may perform operations locally for the logical device. Such operations may include allocating global memory for use with the logical device from only a global memory portion that is local to the primary director. The global memory may be a distributed global memory including memory from multiple directors and possibly multiple engines. Cached data for the logical device may be mirrored automatically by the data storage system. Alternatively, the cached data for the logical device may be mirrored using a host-based mirroring technique.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title High performance logical device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T14%3A42%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Cartmell,%20Jerome&rft.date=2019-08-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10372345B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true