Selective contact etch for unmerged epitaxial source/drain regions

A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surface...

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Hauptverfasser: Reznicek, Alexander, Mehta, Sanjay C
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Mehta, Sanjay C
description A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10366988B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10366988B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10366988B23</originalsourceid><addsrcrecordid>eNqNyk0OgjAQBtBuXBj1DuMBjD8kBLcQjXt0TSbDBzQpbdMOxuO78QCu3uatTd3CQdS-QRK8sihBZaIhJFr8jDSiJ0Sr_LHsKIclCY59YuspYbTB561ZDewydj83Zn-_PZvHATF0yJEFHtq92vOpKMtrVdWX4p_zBWyYMqc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Selective contact etch for unmerged epitaxial source/drain regions</title><source>esp@cenet</source><creator>Reznicek, Alexander ; Mehta, Sanjay C</creator><creatorcontrib>Reznicek, Alexander ; Mehta, Sanjay C</creatorcontrib><description>A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190730&amp;DB=EPODOC&amp;CC=US&amp;NR=10366988B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190730&amp;DB=EPODOC&amp;CC=US&amp;NR=10366988B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Reznicek, Alexander</creatorcontrib><creatorcontrib>Mehta, Sanjay C</creatorcontrib><title>Selective contact etch for unmerged epitaxial source/drain regions</title><description>A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyk0OgjAQBtBuXBj1DuMBjD8kBLcQjXt0TSbDBzQpbdMOxuO78QCu3uatTd3CQdS-QRK8sihBZaIhJFr8jDSiJ0Sr_LHsKIclCY59YuspYbTB561ZDewydj83Zn-_PZvHATF0yJEFHtq92vOpKMtrVdWX4p_zBWyYMqc</recordid><startdate>20190730</startdate><enddate>20190730</enddate><creator>Reznicek, Alexander</creator><creator>Mehta, Sanjay C</creator><scope>EVB</scope></search><sort><creationdate>20190730</creationdate><title>Selective contact etch for unmerged epitaxial source/drain regions</title><author>Reznicek, Alexander ; Mehta, Sanjay C</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10366988B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Reznicek, Alexander</creatorcontrib><creatorcontrib>Mehta, Sanjay C</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Reznicek, Alexander</au><au>Mehta, Sanjay C</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Selective contact etch for unmerged epitaxial source/drain regions</title><date>2019-07-30</date><risdate>2019</risdate><abstract>A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Selective contact etch for unmerged epitaxial source/drain regions
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T22%3A07%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Reznicek,%20Alexander&rft.date=2019-07-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10366988B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true