Devices and methods of reducing damage during BEOL M1 integration

Devices and methods of reducing damage during BEOL M1 integration

Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film st...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Km Mahalingam, Anbu Selvam, Child, Jr., Craig Michael, Chandrashekar, Ashwini
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Km Mahalingam, Anbu Selvam
Child, Jr., Craig Michael
Chandrashekar, Ashwini
description Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10340177B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10340177B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10340177B23</originalsourceid><addsrcrecordid>eNrjZHB0SS3LTE4tVkjMS1HITS3JyE8pVshPUyhKTSlNzsxLV0hJzE1MT1VIKS0C8Zxc_X0UfA0VMvNKUtOLEksy8_N4GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFicmpeakl8aLChgbGJgaG5uZORMTFqAIPpMKY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Devices and methods of reducing damage during BEOL M1 integration</title><source>esp@cenet</source><creator>Km Mahalingam, Anbu Selvam ; Child, Jr., Craig Michael ; Chandrashekar, Ashwini</creator><creatorcontrib>Km Mahalingam, Anbu Selvam ; Child, Jr., Craig Michael ; Chandrashekar, Ashwini</creatorcontrib><description>Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190702&amp;DB=EPODOC&amp;CC=US&amp;NR=10340177B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190702&amp;DB=EPODOC&amp;CC=US&amp;NR=10340177B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Km Mahalingam, Anbu Selvam</creatorcontrib><creatorcontrib>Child, Jr., Craig Michael</creatorcontrib><creatorcontrib>Chandrashekar, Ashwini</creatorcontrib><title>Devices and methods of reducing damage during BEOL M1 integration</title><description>Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHB0SS3LTE4tVkjMS1HITS3JyE8pVshPUyhKTSlNzsxLV0hJzE1MT1VIKS0C8Zxc_X0UfA0VMvNKUtOLEksy8_N4GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFicmpeakl8aLChgbGJgaG5uZORMTFqAIPpMKY</recordid><startdate>20190702</startdate><enddate>20190702</enddate><creator>Km Mahalingam, Anbu Selvam</creator><creator>Child, Jr., Craig Michael</creator><creator>Chandrashekar, Ashwini</creator><scope>EVB</scope></search><sort><creationdate>20190702</creationdate><title>Devices and methods of reducing damage during BEOL M1 integration</title><author>Km Mahalingam, Anbu Selvam ; Child, Jr., Craig Michael ; Chandrashekar, Ashwini</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10340177B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Km Mahalingam, Anbu Selvam</creatorcontrib><creatorcontrib>Child, Jr., Craig Michael</creatorcontrib><creatorcontrib>Chandrashekar, Ashwini</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Km Mahalingam, Anbu Selvam</au><au>Child, Jr., Craig Michael</au><au>Chandrashekar, Ashwini</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Devices and methods of reducing damage during BEOL M1 integration</title><date>2019-07-02</date><risdate>2019</risdate><abstract>Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US10340177B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Devices and methods of reducing damage during BEOL M1 integration
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T22%3A35%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Km%20Mahalingam,%20Anbu%20Selvam&rft.date=2019-07-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10340177B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true