Interconnect structure and fabricating method thereof

An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and expose...

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Hauptverfasser: Kong, De-Jin, Feng, Ji, Zhang, Keen, Li, Yun-Fei, Tey, Ching-Hwa, Feng, Jing, Zhang, Guo-Hai
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Feng, Ji
Zhang, Keen
Li, Yun-Fei
Tey, Ching-Hwa
Feng, Jing
Zhang, Guo-Hai
description An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10332839B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10332839B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10332839B23</originalsourceid><addsrcrecordid>eNrjZDD1zCtJLUrOz8tLTS5RKC4pKk0uKS1KVUjMS1FIS0wqykxOLMnMS1fITS3JyE9RKMlILUrNT-NhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYGxsZGFsaWTkbGxKgBALAELeI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Interconnect structure and fabricating method thereof</title><source>esp@cenet</source><creator>Kong, De-Jin ; Feng, Ji ; Zhang, Keen ; Li, Yun-Fei ; Tey, Ching-Hwa ; Feng, Jing ; Zhang, Guo-Hai</creator><creatorcontrib>Kong, De-Jin ; Feng, Ji ; Zhang, Keen ; Li, Yun-Fei ; Tey, Ching-Hwa ; Feng, Jing ; Zhang, Guo-Hai</creatorcontrib><description>An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190625&amp;DB=EPODOC&amp;CC=US&amp;NR=10332839B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190625&amp;DB=EPODOC&amp;CC=US&amp;NR=10332839B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kong, De-Jin</creatorcontrib><creatorcontrib>Feng, Ji</creatorcontrib><creatorcontrib>Zhang, Keen</creatorcontrib><creatorcontrib>Li, Yun-Fei</creatorcontrib><creatorcontrib>Tey, Ching-Hwa</creatorcontrib><creatorcontrib>Feng, Jing</creatorcontrib><creatorcontrib>Zhang, Guo-Hai</creatorcontrib><title>Interconnect structure and fabricating method thereof</title><description>An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD1zCtJLUrOz8tLTS5RKC4pKk0uKS1KVUjMS1FIS0wqykxOLMnMS1fITS3JyE9RKMlILUrNT-NhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYGxsZGFsaWTkbGxKgBALAELeI</recordid><startdate>20190625</startdate><enddate>20190625</enddate><creator>Kong, De-Jin</creator><creator>Feng, Ji</creator><creator>Zhang, Keen</creator><creator>Li, Yun-Fei</creator><creator>Tey, Ching-Hwa</creator><creator>Feng, Jing</creator><creator>Zhang, Guo-Hai</creator><scope>EVB</scope></search><sort><creationdate>20190625</creationdate><title>Interconnect structure and fabricating method thereof</title><author>Kong, De-Jin ; Feng, Ji ; Zhang, Keen ; Li, Yun-Fei ; Tey, Ching-Hwa ; Feng, Jing ; Zhang, Guo-Hai</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10332839B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Kong, De-Jin</creatorcontrib><creatorcontrib>Feng, Ji</creatorcontrib><creatorcontrib>Zhang, Keen</creatorcontrib><creatorcontrib>Li, Yun-Fei</creatorcontrib><creatorcontrib>Tey, Ching-Hwa</creatorcontrib><creatorcontrib>Feng, Jing</creatorcontrib><creatorcontrib>Zhang, Guo-Hai</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kong, De-Jin</au><au>Feng, Ji</au><au>Zhang, Keen</au><au>Li, Yun-Fei</au><au>Tey, Ching-Hwa</au><au>Feng, Jing</au><au>Zhang, Guo-Hai</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Interconnect structure and fabricating method thereof</title><date>2019-06-25</date><risdate>2019</risdate><abstract>An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Interconnect structure and fabricating method thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T19%3A55%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kong,%20De-Jin&rft.date=2019-06-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10332839B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true