Memory control circuit and memory test method

A memory control circuit, coupled to a multi-channel memory, includes a plurality of channel controllers coupled to respective channel memories of the multi-channel memory, and a built-in self-test (BIST) circuit. The BIST circuit includes a BIST controller and a plurality of command index registers...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Wu, Kuan-Te, Li, Jin-Fu, Lo, Chih-Yen, Lai, Jenn-Shiang
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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