Hybrid atomicity support for a binary translation based microprocessor

A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first shadow register and the second shadow register, to receive a sequence of instructions comprising a first local commit marker, a first global com...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Mekkat, Vineeth, Agron, Jason M, Wu, Youfeng
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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