System, method, and computer program product for property clustering associated with formal verification of an electronic circuit design
The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-example...
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| creator | Nunes Barcelos, Ronalu Augusta de Sousa Carmo, Glauber Tadeu Mafra, Augusto Amaral Fonseca, Regina Mara Amaral Crepalde, Mirlaine Aparecida de Sousa Santos, Guilherme Henrique Reckziegel, Lucas Luz Júnior, Valdir Antoniazzi de Oliveira, Hudson Dyele Pinheiro |
| description | The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity. |
| format | Patent |
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| subjects | CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | System, method, and computer program product for property clustering associated with formal verification of an electronic circuit design |
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