Semiconductor devices and methods of fabricating the same

Semiconductor devices and methods of fabricating the same

A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern cov...

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Hauptverfasser: Ko, Seung Pil, Lee, Kilho, Jeong, Daeeun, Suh, Kiseok
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Ko, Seung Pil
Lee, Kilho
Jeong, Daeeun
Suh, Kiseok
description A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10283698B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10283698B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10283698B23</originalsourceid><addsrcrecordid>eNrjZLAMTs3NTM7PSylNLskvUkhJLctMTi1WSMxLUchNLcnITylWyE9TSEtMKspMTizJzEtXKMlIVShOzE3lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGBkYWxmaWFk5GxsSoAQBMOS7d</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor devices and methods of fabricating the same</title><source>esp@cenet</source><creator>Ko, Seung Pil ; Lee, Kilho ; Jeong, Daeeun ; Suh, Kiseok</creator><creatorcontrib>Ko, Seung Pil ; Lee, Kilho ; Jeong, Daeeun ; Suh, Kiseok</creatorcontrib><description>A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190507&amp;DB=EPODOC&amp;CC=US&amp;NR=10283698B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190507&amp;DB=EPODOC&amp;CC=US&amp;NR=10283698B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ko, Seung Pil</creatorcontrib><creatorcontrib>Lee, Kilho</creatorcontrib><creatorcontrib>Jeong, Daeeun</creatorcontrib><creatorcontrib>Suh, Kiseok</creatorcontrib><title>Semiconductor devices and methods of fabricating the same</title><description>A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAMTs3NTM7PSylNLskvUkhJLctMTi1WSMxLUchNLcnITylWyE9TSEtMKspMTizJzEtXKMlIVShOzE3lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGBkYWxmaWFk5GxsSoAQBMOS7d</recordid><startdate>20190507</startdate><enddate>20190507</enddate><creator>Ko, Seung Pil</creator><creator>Lee, Kilho</creator><creator>Jeong, Daeeun</creator><creator>Suh, Kiseok</creator><scope>EVB</scope></search><sort><creationdate>20190507</creationdate><title>Semiconductor devices and methods of fabricating the same</title><author>Ko, Seung Pil ; Lee, Kilho ; Jeong, Daeeun ; Suh, Kiseok</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10283698B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Ko, Seung Pil</creatorcontrib><creatorcontrib>Lee, Kilho</creatorcontrib><creatorcontrib>Jeong, Daeeun</creatorcontrib><creatorcontrib>Suh, Kiseok</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ko, Seung Pil</au><au>Lee, Kilho</au><au>Jeong, Daeeun</au><au>Suh, Kiseok</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor devices and methods of fabricating the same</title><date>2019-05-07</date><risdate>2019</risdate><abstract>A device, which may include a semiconductor device, may include a contact plug, a first barrier metal covering a bottom surface of the contact plug and a lower sidewall of the contact plug, such that the first barrier metal exposes an upper sidewall of the contact plug, and an insulation pattern covering the upper sidewall of the contact plug such that the insulation pattern isolates the first barrier metal from exposure. A magnetic tunnel junction pattern may cover a top surface of the contact plug. Each element of the contact plug, the first barrier metal, and the insulation pattern may be in a contact hole of a first interlayer dielectric layer.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor devices and methods of fabricating the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T18%3A04%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ko,%20Seung%20Pil&rft.date=2019-05-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10283698B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true