Technologies for managing power during an activation cycle

Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce...

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Hauptverfasser:	Ramachandran, Aswin, Raman, Arvind
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	Ramachandran, Aswin Raman, Arvind
description	Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10261572B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10261572B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10261572B23</originalsourceid><addsrcrecordid>eNrjZLAKSU3OyMvPyU_PTC1WSMsvUshNzEtMz8xLVyjIL08tUkgpLQJxEvMUEpNLMssSSzLz8xSSK5NzUnkYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxosKGBkZmhqbmRk5ExMWoAknYvWQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Technologies for managing power during an activation cycle</title><source>esp@cenet</source><creator>Ramachandran, Aswin ; Raman, Arvind</creator><creatorcontrib>Ramachandran, Aswin ; Raman, Arvind</creatorcontrib><description>Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190416&DB=EPODOC&CC=US&NR=10261572B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190416&DB=EPODOC&CC=US&NR=10261572B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ramachandran, Aswin</creatorcontrib><creatorcontrib>Raman, Arvind</creatorcontrib><title>Technologies for managing power during an activation cycle</title><description>Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAKSU3OyMvPyU_PTC1WSMsvUshNzEtMz8xLVyjIL08tUkgpLQJxEvMUEpNLMssSSzLz8xSSK5NzUnkYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQWJyal5qSXxosKGBkZmhqbmRk5ExMWoAknYvWQ</recordid><startdate>20190416</startdate><enddate>20190416</enddate><creator>Ramachandran, Aswin</creator><creator>Raman, Arvind</creator><scope>EVB</scope></search><sort><creationdate>20190416</creationdate><title>Technologies for managing power during an activation cycle</title><author>Ramachandran, Aswin ; Raman, Arvind</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10261572B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Ramachandran, Aswin</creatorcontrib><creatorcontrib>Raman, Arvind</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ramachandran, Aswin</au><au>Raman, Arvind</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Technologies for managing power during an activation cycle</title><date>2019-04-16</date><risdate>2019</risdate><abstract>Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Technologies for managing power during an activation cycle
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-14T20%3A25%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ramachandran,%20Aswin&rft.date=2019-04-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10261572B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true