Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to...
Gespeichert in:
| Hauptverfasser: | , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Yonehama, Keisuke Shimura, Yasuhiro Higashi, Tomoki Kijima, Junichi Ohtsuki, Sumito Oosera, Shinichi Oda, Tomohiro |
| description | According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10255979B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10255979B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10255979B13</originalsourceid><addsrcrecordid>eNrjZJAOTs3NTM7PSylNLskvUshNzc0vqlRISS3LTE7lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGBkamppbmlk6GxsSoAQCa4yPo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor memory device</title><source>esp@cenet</source><creator>Yonehama, Keisuke ; Shimura, Yasuhiro ; Higashi, Tomoki ; Kijima, Junichi ; Ohtsuki, Sumito ; Oosera, Shinichi ; Oda, Tomohiro</creator><creatorcontrib>Yonehama, Keisuke ; Shimura, Yasuhiro ; Higashi, Tomoki ; Kijima, Junichi ; Ohtsuki, Sumito ; Oosera, Shinichi ; Oda, Tomohiro</creatorcontrib><description>According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190409&DB=EPODOC&CC=US&NR=10255979B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190409&DB=EPODOC&CC=US&NR=10255979B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Yonehama, Keisuke</creatorcontrib><creatorcontrib>Shimura, Yasuhiro</creatorcontrib><creatorcontrib>Higashi, Tomoki</creatorcontrib><creatorcontrib>Kijima, Junichi</creatorcontrib><creatorcontrib>Ohtsuki, Sumito</creatorcontrib><creatorcontrib>Oosera, Shinichi</creatorcontrib><creatorcontrib>Oda, Tomohiro</creatorcontrib><title>Semiconductor memory device</title><description>According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAOTs3NTM7PSylNLskvUshNzc0vqlRISS3LTE7lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGBkamppbmlk6GxsSoAQCa4yPo</recordid><startdate>20190409</startdate><enddate>20190409</enddate><creator>Yonehama, Keisuke</creator><creator>Shimura, Yasuhiro</creator><creator>Higashi, Tomoki</creator><creator>Kijima, Junichi</creator><creator>Ohtsuki, Sumito</creator><creator>Oosera, Shinichi</creator><creator>Oda, Tomohiro</creator><scope>EVB</scope></search><sort><creationdate>20190409</creationdate><title>Semiconductor memory device</title><author>Yonehama, Keisuke ; Shimura, Yasuhiro ; Higashi, Tomoki ; Kijima, Junichi ; Ohtsuki, Sumito ; Oosera, Shinichi ; Oda, Tomohiro</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10255979B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Yonehama, Keisuke</creatorcontrib><creatorcontrib>Shimura, Yasuhiro</creatorcontrib><creatorcontrib>Higashi, Tomoki</creatorcontrib><creatorcontrib>Kijima, Junichi</creatorcontrib><creatorcontrib>Ohtsuki, Sumito</creatorcontrib><creatorcontrib>Oosera, Shinichi</creatorcontrib><creatorcontrib>Oda, Tomohiro</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yonehama, Keisuke</au><au>Shimura, Yasuhiro</au><au>Higashi, Tomoki</au><au>Kijima, Junichi</au><au>Ohtsuki, Sumito</au><au>Oosera, Shinichi</au><au>Oda, Tomohiro</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor memory device</title><date>2019-04-09</date><risdate>2019</risdate><abstract>According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US10255979B1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Semiconductor memory device |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-19T08%3A30%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Yonehama,%20Keisuke&rft.date=2019-04-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10255979B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |