Circuit design having aligned power staples
A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Lin, Irene Y. L Yuan, Lei Rashed, Mahbub |
| description | A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10242946B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10242946B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10242946B23</originalsourceid><addsrcrecordid>eNrjZNB2zixKLs0sUUhJLc5Mz1PISCzLzEtXSMwBclJTFAryy1OLFIpLEgtyUot5GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFicmpeakl8aLChgZGJkaWJmZORMTFqAGxKKaU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Circuit design having aligned power staples</title><source>esp@cenet</source><creator>Lin, Irene Y. L ; Yuan, Lei ; Rashed, Mahbub</creator><creatorcontrib>Lin, Irene Y. L ; Yuan, Lei ; Rashed, Mahbub</creatorcontrib><description>A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190326&DB=EPODOC&CC=US&NR=10242946B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190326&DB=EPODOC&CC=US&NR=10242946B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lin, Irene Y. L</creatorcontrib><creatorcontrib>Yuan, Lei</creatorcontrib><creatorcontrib>Rashed, Mahbub</creatorcontrib><title>Circuit design having aligned power staples</title><description>A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB2zixKLs0sUUhJLc5Mz1PISCzLzEtXSMwBclJTFAryy1OLFIpLEgtyUot5GFjTEnOKU3mhNDeDoptriLOHbmpBfnxqcUFicmpeakl8aLChgZGJkaWJmZORMTFqAGxKKaU</recordid><startdate>20190326</startdate><enddate>20190326</enddate><creator>Lin, Irene Y. L</creator><creator>Yuan, Lei</creator><creator>Rashed, Mahbub</creator><scope>EVB</scope></search><sort><creationdate>20190326</creationdate><title>Circuit design having aligned power staples</title><author>Lin, Irene Y. L ; Yuan, Lei ; Rashed, Mahbub</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10242946B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lin, Irene Y. L</creatorcontrib><creatorcontrib>Yuan, Lei</creatorcontrib><creatorcontrib>Rashed, Mahbub</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lin, Irene Y. L</au><au>Yuan, Lei</au><au>Rashed, Mahbub</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Circuit design having aligned power staples</title><date>2019-03-26</date><risdate>2019</risdate><abstract>A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US10242946B2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | Circuit design having aligned power staples |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T06%3A46%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lin,%20Irene%20Y.%20L&rft.date=2019-03-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10242946B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |