Clock generation for integrated circuit testing

A disclosed integrated circuit includes first and second clock generation circuits, a stagger circuit, and a plurality of scan chains. The first clock generation circuit receives a first clock signal and generates a first set of clock pulses having a first frequency in response to receipt of a first...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Hartanto, Ismed D, Chauhan, Pranjal, Shivaray, Banadappa V, Warshofsky, Alex S
Format: Patent
Sprache:eng
Schlagworte:
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