Method for simultaneous modification of multiple semiconductor device features

Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned w...

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Hauptverfasser: Zortman, William A, Larson, Kurt W, Shul, Randy J, Sniegowski, Jeffry J
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creator Zortman, William A
Larson, Kurt W
Shul, Randy J
Sniegowski, Jeffry J
description Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10217704B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10217704B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10217704B13</originalsourceid><addsrcrecordid>eNqNizEKAjEUBdNYiHqH7wGEjQrbK4qNNmq9hOSF_ZDkh03i-VXwAFZTzMxc3a6oozjyMlHh2EI1CdIKRXHs2ZrKkkg8fRXnACqIbCW5ZuvncXixBXmY2iaUpZp5EwpWPy7U-nx6HC8bZBlQsrFIqMPzrrut7vtuf9C7f5o3llw3qQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for simultaneous modification of multiple semiconductor device features</title><source>esp@cenet</source><creator>Zortman, William A ; Larson, Kurt W ; Shul, Randy J ; Sniegowski, Jeffry J</creator><creatorcontrib>Zortman, William A ; Larson, Kurt W ; Shul, Randy J ; Sniegowski, Jeffry J</creatorcontrib><description>Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190226&amp;DB=EPODOC&amp;CC=US&amp;NR=10217704B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190226&amp;DB=EPODOC&amp;CC=US&amp;NR=10217704B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Zortman, William A</creatorcontrib><creatorcontrib>Larson, Kurt W</creatorcontrib><creatorcontrib>Shul, Randy J</creatorcontrib><creatorcontrib>Sniegowski, Jeffry J</creatorcontrib><title>Method for simultaneous modification of multiple semiconductor device features</title><description>Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNizEKAjEUBdNYiHqH7wGEjQrbK4qNNmq9hOSF_ZDkh03i-VXwAFZTzMxc3a6oozjyMlHh2EI1CdIKRXHs2ZrKkkg8fRXnACqIbCW5ZuvncXixBXmY2iaUpZp5EwpWPy7U-nx6HC8bZBlQsrFIqMPzrrut7vtuf9C7f5o3llw3qQ</recordid><startdate>20190226</startdate><enddate>20190226</enddate><creator>Zortman, William A</creator><creator>Larson, Kurt W</creator><creator>Shul, Randy J</creator><creator>Sniegowski, Jeffry J</creator><scope>EVB</scope></search><sort><creationdate>20190226</creationdate><title>Method for simultaneous modification of multiple semiconductor device features</title><author>Zortman, William A ; Larson, Kurt W ; Shul, Randy J ; Sniegowski, Jeffry J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10217704B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Zortman, William A</creatorcontrib><creatorcontrib>Larson, Kurt W</creatorcontrib><creatorcontrib>Shul, Randy J</creatorcontrib><creatorcontrib>Sniegowski, Jeffry J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zortman, William A</au><au>Larson, Kurt W</au><au>Shul, Randy J</au><au>Sniegowski, Jeffry J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for simultaneous modification of multiple semiconductor device features</title><date>2019-02-26</date><risdate>2019</risdate><abstract>Various technologies for simultaneously making a plurality of modifications to a previously manufactured semiconductor are described herein. A mask layer is applied to a surface of the previously manufactured semiconductor device. A pattern is formed in the mask layer, where the pattern is aligned with a plurality of features of the semiconductor device that are desirably modified. Layers of the semiconductor device are etched based on the pattern to create a plurality of vias that each extend through one or more layers of the semiconductor device to a respective feature of the device. A conducting material is deposited into the vias to form a plurality of conducting plugs. Conducting material may be further deposited on the surface of the semiconductor device to connect plugs to one another and/or connect plugs to surface features of the device, thereby forming a plurality of new connections between features of the semiconductor device.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
title Method for simultaneous modification of multiple semiconductor device features
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T08%3A12%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Zortman,%20William%20A&rft.date=2019-02-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10217704B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true