Verification of photonic integrated circuits

Verification of photonic integrated circuits

Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. The...

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Hauptverfasser: Ferguson, John G, Cayo, John D, Arriordaz, Alexandre, Cao, Ruping
Format: Patent
Sprache:eng
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CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Ferguson, John G
Cayo, John D
Arriordaz, Alexandre
Cao, Ruping
description Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Verification of photonic integrated circuits
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