Liner recess for fully aligned via
Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each met...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Ryan, Errol Todd Lin, Sean Xuan |
description | Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10181421B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10181421B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10181421B13</originalsourceid><addsrcrecordid>eNrjZFDyycxLLVIoSk1OLS5WSMsvUkgrzcmpVEjMyUzPS01RKMtM5GFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgaGFoYmRoZOhsbEqAEAkfYlxQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Liner recess for fully aligned via</title><source>esp@cenet</source><creator>Ryan, Errol Todd ; Lin, Sean Xuan</creator><creatorcontrib>Ryan, Errol Todd ; Lin, Sean Xuan</creatorcontrib><description>Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190115&DB=EPODOC&CC=US&NR=10181421B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190115&DB=EPODOC&CC=US&NR=10181421B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ryan, Errol Todd</creatorcontrib><creatorcontrib>Lin, Sean Xuan</creatorcontrib><title>Liner recess for fully aligned via</title><description>Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDyycxLLVIoSk1OLS5WSMsvUkgrzcmpVEjMyUzPS01RKMtM5GFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8aHBhgaGFoYmRoZOhsbEqAEAkfYlxQ</recordid><startdate>20190115</startdate><enddate>20190115</enddate><creator>Ryan, Errol Todd</creator><creator>Lin, Sean Xuan</creator><scope>EVB</scope></search><sort><creationdate>20190115</creationdate><title>Liner recess for fully aligned via</title><author>Ryan, Errol Todd ; Lin, Sean Xuan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10181421B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Ryan, Errol Todd</creatorcontrib><creatorcontrib>Lin, Sean Xuan</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ryan, Errol Todd</au><au>Lin, Sean Xuan</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Liner recess for fully aligned via</title><date>2019-01-15</date><risdate>2019</risdate><abstract>Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US10181421B1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Liner recess for fully aligned via |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T03%3A59%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ryan,%20Errol%20Todd&rft.date=2019-01-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10181421B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |