Method of manufacturing electronic component module and electronic component module
A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surfa...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Satake, Yoshiaki Kiyono, Shinya |
| description | A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10177108B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10177108B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10177108B23</originalsourceid><addsrcrecordid>eNrjZAj2TS3JyE9RyE9TyE3MK01LTC4pLcrMS1dIzUlNLinKz8tMVkjOzy3Iz0vNK1HIzU8pzUlVSMxLwSfPw8CalphTnMoLpbkZFN1cQ5w9dFML8uNTiwsSk1PzUkviQ4MNDQzNzQ0NLJyMjIlRAwC-Ujlf</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of manufacturing electronic component module and electronic component module</title><source>esp@cenet</source><creator>Satake, Yoshiaki ; Kiyono, Shinya</creator><creatorcontrib>Satake, Yoshiaki ; Kiyono, Shinya</creatorcontrib><description>A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ; TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190108&DB=EPODOC&CC=US&NR=10177108B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190108&DB=EPODOC&CC=US&NR=10177108B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Satake, Yoshiaki</creatorcontrib><creatorcontrib>Kiyono, Shinya</creatorcontrib><title>Method of manufacturing electronic component module and electronic component module</title><description>A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><subject>TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAj2TS3JyE9RyE9TyE3MK01LTC4pLcrMS1dIzUlNLinKz8tMVkjOzy3Iz0vNK1HIzU8pzUlVSMxLwSfPw8CalphTnMoLpbkZFN1cQ5w9dFML8uNTiwsSk1PzUkviQ4MNDQzNzQ0NLJyMjIlRAwC-Ujlf</recordid><startdate>20190108</startdate><enddate>20190108</enddate><creator>Satake, Yoshiaki</creator><creator>Kiyono, Shinya</creator><scope>EVB</scope></search><sort><creationdate>20190108</creationdate><title>Method of manufacturing electronic component module and electronic component module</title><author>Satake, Yoshiaki ; Kiyono, Shinya</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10177108B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><topic>TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE</topic><toplevel>online_resources</toplevel><creatorcontrib>Satake, Yoshiaki</creatorcontrib><creatorcontrib>Kiyono, Shinya</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Satake, Yoshiaki</au><au>Kiyono, Shinya</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of manufacturing electronic component module and electronic component module</title><date>2019-01-08</date><risdate>2019</risdate><abstract>A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US10177108B2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION ORPROCESSING OF GOODS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINSTCLIMATE CHANGE |
| title | Method of manufacturing electronic component module and electronic component module |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T21%3A05%3A22IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Satake,%20Yoshiaki&rft.date=2019-01-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10177108B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |