Methods of forming a vertical transistor device

One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Bentley, Steven J, Fronheiser, Jody A, Xie, Ruilong
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!