Managing frequency changes of clock signals across different clock domains

A processor maintains a minimum setup time for data being transferred between clock domains, including maintaining the minimum setup time in response to a frequency change in a clock signal for at least one of the clock domains. The processor employs one or more control modules that monitor clock ed...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kommrusch, Steven, Mehra, Amitabh, Born, Richard Martin
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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