Phase-inverted clock generation circuit and register

A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and t...

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Bibliographische Detailangaben
Hauptverfasser: Zeng, Qiuling, Chen, Qi, Xia, Yu, Zhong, Jianfu
Format: Patent
Sprache:eng
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