Structure and method for overlay marks
A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semicondu...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Chen, Chun-Kuang Wen, Ming-Chang Wang, Hsien-Cheng Ku, Yao-Ching |
description | A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10163738B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10163738B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10163738B23</originalsourceid><addsrcrecordid>eNrjZFALLikqTS4pLUpVSMxLUchNLcnIT1FIyy9SyC9LLcpJrFTITSzKLuZhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYGhmbG5sYWTkbGxKgBAHzpJ8c</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Structure and method for overlay marks</title><source>esp@cenet</source><creator>Chen, Chun-Kuang ; Wen, Ming-Chang ; Wang, Hsien-Cheng ; Ku, Yao-Ching</creator><creatorcontrib>Chen, Chun-Kuang ; Wen, Ming-Chang ; Wang, Hsien-Cheng ; Ku, Yao-Ching</creatorcontrib><description>A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.</description><language>eng</language><subject>APPARATUS SPECIALLY ADAPTED THEREFOR ; BASIC ELECTRIC ELEMENTS ; CINEMATOGRAPHY ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; ELECTROGRAPHY ; HOLOGRAPHY ; MATERIALS THEREFOR ; ORIGINALS THEREFOR ; PHOTOGRAPHY ; PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181225&DB=EPODOC&CC=US&NR=10163738B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181225&DB=EPODOC&CC=US&NR=10163738B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chen, Chun-Kuang</creatorcontrib><creatorcontrib>Wen, Ming-Chang</creatorcontrib><creatorcontrib>Wang, Hsien-Cheng</creatorcontrib><creatorcontrib>Ku, Yao-Ching</creatorcontrib><title>Structure and method for overlay marks</title><description>A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.</description><subject>APPARATUS SPECIALLY ADAPTED THEREFOR</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CINEMATOGRAPHY</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>ELECTROGRAPHY</subject><subject>HOLOGRAPHY</subject><subject>MATERIALS THEREFOR</subject><subject>ORIGINALS THEREFOR</subject><subject>PHOTOGRAPHY</subject><subject>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFALLikqTS4pLUpVSMxLUchNLcnIT1FIyy9SyC9LLcpJrFTITSzKLuZhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYYGhmbG5sYWTkbGxKgBAHzpJ8c</recordid><startdate>20181225</startdate><enddate>20181225</enddate><creator>Chen, Chun-Kuang</creator><creator>Wen, Ming-Chang</creator><creator>Wang, Hsien-Cheng</creator><creator>Ku, Yao-Ching</creator><scope>EVB</scope></search><sort><creationdate>20181225</creationdate><title>Structure and method for overlay marks</title><author>Chen, Chun-Kuang ; Wen, Ming-Chang ; Wang, Hsien-Cheng ; Ku, Yao-Ching</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10163738B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>APPARATUS SPECIALLY ADAPTED THEREFOR</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CINEMATOGRAPHY</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>ELECTROGRAPHY</topic><topic>HOLOGRAPHY</topic><topic>MATERIALS THEREFOR</topic><topic>ORIGINALS THEREFOR</topic><topic>PHOTOGRAPHY</topic><topic>PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Chen, Chun-Kuang</creatorcontrib><creatorcontrib>Wen, Ming-Chang</creatorcontrib><creatorcontrib>Wang, Hsien-Cheng</creatorcontrib><creatorcontrib>Ku, Yao-Ching</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chen, Chun-Kuang</au><au>Wen, Ming-Chang</au><au>Wang, Hsien-Cheng</au><au>Ku, Yao-Ching</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Structure and method for overlay marks</title><date>2018-12-25</date><risdate>2018</risdate><abstract>A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US10163738B2 |
source | esp@cenet |
subjects | APPARATUS SPECIALLY ADAPTED THEREFOR BASIC ELECTRIC ELEMENTS CINEMATOGRAPHY ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY ELECTROGRAPHY HOLOGRAPHY MATERIALS THEREFOR ORIGINALS THEREFOR PHOTOGRAPHY PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES PHYSICS SEMICONDUCTOR DEVICES |
title | Structure and method for overlay marks |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-19T13%3A15%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chen,%20Chun-Kuang&rft.date=2018-12-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10163738B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |