Method and apparatus for performing logical compare operations
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical com...
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| creator | Kapoor, Rajiv Buxton, Mark Gottlieb, Koby Zohar, Ronen Sperber, Zeev |
| description | A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location. |
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In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181204&DB=EPODOC&CC=US&NR=10146536B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181204&DB=EPODOC&CC=US&NR=10146536B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kapoor, Rajiv</creatorcontrib><creatorcontrib>Buxton, Mark</creatorcontrib><creatorcontrib>Gottlieb, Koby</creatorcontrib><creatorcontrib>Zohar, Ronen</creatorcontrib><creatorcontrib>Sperber, Zeev</creatorcontrib><title>Method and apparatus for performing logical compare operations</title><description>A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDzTS3JyE9RSMwD4oKCxKLEktJihbT8IoWC1CIglZuZl66Qk5-emZyYo5CcnwtUkaqQD5RLLMnMzyvmYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGBoYmZqbGZk5GxsSoAQCBrTEY</recordid><startdate>20181204</startdate><enddate>20181204</enddate><creator>Kapoor, Rajiv</creator><creator>Buxton, Mark</creator><creator>Gottlieb, Koby</creator><creator>Zohar, Ronen</creator><creator>Sperber, Zeev</creator><scope>EVB</scope></search><sort><creationdate>20181204</creationdate><title>Method and apparatus for performing logical compare operations</title><author>Kapoor, Rajiv ; Buxton, Mark ; Gottlieb, Koby ; Zohar, Ronen ; Sperber, Zeev</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10146536B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Kapoor, Rajiv</creatorcontrib><creatorcontrib>Buxton, Mark</creatorcontrib><creatorcontrib>Gottlieb, Koby</creatorcontrib><creatorcontrib>Zohar, Ronen</creatorcontrib><creatorcontrib>Sperber, Zeev</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kapoor, Rajiv</au><au>Buxton, Mark</au><au>Gottlieb, Koby</au><au>Zohar, Ronen</au><au>Sperber, Zeev</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method and apparatus for performing logical compare operations</title><date>2018-12-04</date><risdate>2018</risdate><abstract>A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Method and apparatus for performing logical compare operations |
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