Hierarchical flash translation layer structure and method for designing the same

A Flash Translation Layer (FTL) structure including mapping information for storing data is disclosed. The FTL structure includes a plurality of hierarchical data groups including a zeroth-layer host data group, and first-layer to nth-layer metadata groups, and zeroth to nth logs configured in a hie...

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Bibliographische Detailangaben
Hauptverfasser: Kim, Kijun, Lee, Sunggab, Kim, Hongseok, Seong, Yoon Jae, Choi, Jin-yong, Nam, Eyee Hyun
Format: Patent
Sprache:eng
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Zusammenfassung:A Flash Translation Layer (FTL) structure including mapping information for storing data is disclosed. The FTL structure includes a plurality of hierarchical data groups including a zeroth-layer host data group, and first-layer to nth-layer metadata groups, and zeroth to nth logs configured in a hierarchical structure in correspondence with the respective hierarchical data groups, for processing data of the corresponding data groups. A kth log (0≤k≤n) provides an interface to volatile memory resources dividedly allocated to the kth log, an interface to non-volatile memory resources dividedly allocated to the kth log, and an interface to at least one of (k−1)th and (k+1)th logs.