Silicon package for embedded semiconductor chip and power converter

A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area...

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Hauptverfasser: Lopez, Osvaldo Jorge, Grebs, Tom, Molloy, Simon John, Noquil, Jonathan Almeria
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creator Lopez, Osvaldo Jorge
Grebs, Tom
Molloy, Simon John
Noquil, Jonathan Almeria
description A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10121716B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10121716B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10121716B23</originalsourceid><addsrcrecordid>eNrjZHAOzszJTM7PUyhITM5OTE9VSMsvUkjNTUpNSUlNUShOzQVJppQmlwCFkzMyCxQS81IUCvLLU4Hc_Lyy1KKS1CIeBta0xJziVF4ozc2g6OYa4uyhm1qQH59aDDQ5NS-1JD402NDA0MjQ3NDMyciYGDUAh7oyrQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Silicon package for embedded semiconductor chip and power converter</title><source>esp@cenet</source><creator>Lopez, Osvaldo Jorge ; Grebs, Tom ; Molloy, Simon John ; Noquil, Jonathan Almeria</creator><creatorcontrib>Lopez, Osvaldo Jorge ; Grebs, Tom ; Molloy, Simon John ; Noquil, Jonathan Almeria</creatorcontrib><description>A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20181106&amp;DB=EPODOC&amp;CC=US&amp;NR=10121716B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20181106&amp;DB=EPODOC&amp;CC=US&amp;NR=10121716B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lopez, Osvaldo Jorge</creatorcontrib><creatorcontrib>Grebs, Tom</creatorcontrib><creatorcontrib>Molloy, Simon John</creatorcontrib><creatorcontrib>Noquil, Jonathan Almeria</creatorcontrib><title>Silicon package for embedded semiconductor chip and power converter</title><description>A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAOzszJTM7PUyhITM5OTE9VSMsvUkjNTUpNSUlNUShOzQVJppQmlwCFkzMyCxQS81IUCvLLU4Hc_Lyy1KKS1CIeBta0xJziVF4ozc2g6OYa4uyhm1qQH59aDDQ5NS-1JD402NDA0MjQ3NDMyciYGDUAh7oyrQ</recordid><startdate>20181106</startdate><enddate>20181106</enddate><creator>Lopez, Osvaldo Jorge</creator><creator>Grebs, Tom</creator><creator>Molloy, Simon John</creator><creator>Noquil, Jonathan Almeria</creator><scope>EVB</scope></search><sort><creationdate>20181106</creationdate><title>Silicon package for embedded semiconductor chip and power converter</title><author>Lopez, Osvaldo Jorge ; Grebs, Tom ; Molloy, Simon John ; Noquil, Jonathan Almeria</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10121716B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lopez, Osvaldo Jorge</creatorcontrib><creatorcontrib>Grebs, Tom</creatorcontrib><creatorcontrib>Molloy, Simon John</creatorcontrib><creatorcontrib>Noquil, Jonathan Almeria</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lopez, Osvaldo Jorge</au><au>Grebs, Tom</au><au>Molloy, Simon John</au><au>Noquil, Jonathan Almeria</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Silicon package for embedded semiconductor chip and power converter</title><date>2018-11-06</date><risdate>2018</risdate><abstract>A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Silicon package for embedded semiconductor chip and power converter
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T04%3A58%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Lopez,%20Osvaldo%20Jorge&rft.date=2018-11-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10121716B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true