Method and system for efficient cache buffering in a system having parity arms to enable hardware acceleration

Method and system for efficient cache buffering in a system having parity arms to enable hardware acceleration

A system and method for efficient cache buffering are provided. The disclosed method includes receiving a host command from a host, extracting command information from the host command, determining an Input/Output (I/O) action to be taken in connection with the host command, determining that the I/O...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Veerla, Sridhar Rao, Radhakrishnan, Gowrisankar, Pandit, Panthini, Hoglund, Timothy, Simionescu, Horia
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A system and method for efficient cache buffering are provided. The disclosed method includes receiving a host command from a host, extracting command information from the host command, determining an Input/Output (I/O) action to be taken in connection with the host command, determining that the I/O action spans more than one strip, and based on the I/O action spanning more than one strip, allocating a cache frame anchor for a row on-demand along with a cache frame anchor for a strip to accommodate the I/O action.