Detection of multiple accesses to a row address of a dynamic memory within a refresh period

Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may...

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Bibliographische Detailangaben

Hauptverfasser:	Cheng, Lik, Park, Heechoul, Duncan, Neil, Grohoski, Gregory F, Jeffrey, David, Fang, Clement
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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