Non-volatile semiconductor storage device for reducing the number of memory cells arranged along a control to which a memory gate voltage is applied

A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plura...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Kasai, Hideo, Kawashima, Yasuhiko, Taniguchi, Yasuhiro, Shinagawa, Yutaka, Okuyama, Kosuke, Sakurai, Ryotaro
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
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