Zero detection of a sum of inputs without performing an addition

A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Niekisch, Manuela, Schelm, Kerstin C, Kroener, Michael K, Mueller, Silvia M
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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