Non-interleaved scan operation for achieving higher scan throughput in presence of slower scan outputs

A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scann...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Mittal, Rajesh Kumar, Kawoosa, Mudasir Shafat
Format:	Patent
Sprache:	eng
Schlagworte:	MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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