Method for manufacturing vertical super junction drift layer of power semiconductor devices

Method for manufacturing vertical super junction drift layer of power semiconductor devices

A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing a...

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Hauptverfasser: Gu, Hongming, Zou, Youbiao, Zhang, Bo, Song, Wenlong, Li, Zehong, Song, Xunyi, Zhang, Jinping
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Gu, Hongming
Zou, Youbiao
Zhang, Bo
Song, Wenlong
Li, Zehong
Song, Xunyi
Zhang, Jinping
description A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US10056452B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US10056452B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US10056452B23</originalsourceid><addsrcrecordid>eNqNjDEOwjAQBN1QIOAPxwOQQiA8AASioQIqisg6n4NR4rPscxC_xwUPoNrRaLRT9biQPNmA5QiD9tlqlByd72CkKA51DykHivDKHsWxBxOdFej1p0i2EPhdINHgkL3JKOXI0OiQ0lxNrO4TLX47U8vT8XY4ryhwSyloJE_S3q_rqmp226be15t_mi_elzxt</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for manufacturing vertical super junction drift layer of power semiconductor devices</title><source>esp@cenet</source><creator>Gu, Hongming ; Zou, Youbiao ; Zhang, Bo ; Song, Wenlong ; Li, Zehong ; Song, Xunyi ; Zhang, Jinping</creator><creatorcontrib>Gu, Hongming ; Zou, Youbiao ; Zhang, Bo ; Song, Wenlong ; Li, Zehong ; Song, Xunyi ; Zhang, Jinping</creatorcontrib><description>A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180821&amp;DB=EPODOC&amp;CC=US&amp;NR=10056452B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180821&amp;DB=EPODOC&amp;CC=US&amp;NR=10056452B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Gu, Hongming</creatorcontrib><creatorcontrib>Zou, Youbiao</creatorcontrib><creatorcontrib>Zhang, Bo</creatorcontrib><creatorcontrib>Song, Wenlong</creatorcontrib><creatorcontrib>Li, Zehong</creatorcontrib><creatorcontrib>Song, Xunyi</creatorcontrib><creatorcontrib>Zhang, Jinping</creatorcontrib><title>Method for manufacturing vertical super junction drift layer of power semiconductor devices</title><description>A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjDEOwjAQBN1QIOAPxwOQQiA8AASioQIqisg6n4NR4rPscxC_xwUPoNrRaLRT9biQPNmA5QiD9tlqlByd72CkKA51DykHivDKHsWxBxOdFej1p0i2EPhdINHgkL3JKOXI0OiQ0lxNrO4TLX47U8vT8XY4ryhwSyloJE_S3q_rqmp226be15t_mi_elzxt</recordid><startdate>20180821</startdate><enddate>20180821</enddate><creator>Gu, Hongming</creator><creator>Zou, Youbiao</creator><creator>Zhang, Bo</creator><creator>Song, Wenlong</creator><creator>Li, Zehong</creator><creator>Song, Xunyi</creator><creator>Zhang, Jinping</creator><scope>EVB</scope></search><sort><creationdate>20180821</creationdate><title>Method for manufacturing vertical super junction drift layer of power semiconductor devices</title><author>Gu, Hongming ; Zou, Youbiao ; Zhang, Bo ; Song, Wenlong ; Li, Zehong ; Song, Xunyi ; Zhang, Jinping</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US10056452B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Gu, Hongming</creatorcontrib><creatorcontrib>Zou, Youbiao</creatorcontrib><creatorcontrib>Zhang, Bo</creatorcontrib><creatorcontrib>Song, Wenlong</creatorcontrib><creatorcontrib>Li, Zehong</creatorcontrib><creatorcontrib>Song, Xunyi</creatorcontrib><creatorcontrib>Zhang, Jinping</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gu, Hongming</au><au>Zou, Youbiao</au><au>Zhang, Bo</au><au>Song, Wenlong</au><au>Li, Zehong</au><au>Song, Xunyi</au><au>Zhang, Jinping</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for manufacturing vertical super junction drift layer of power semiconductor devices</title><date>2018-08-21</date><risdate>2018</risdate><abstract>A method for manufacturing a vertical super junction drift layer of a power semiconductor device. The method includes: a): adopting a P+ single crystal silicon to prepare a P+ substrate; b): finishing top processes of the devices on the P+ substrate, forming at least a P type region, manufacturing active area and metallizing the top surface of the P+ substrate; c): thinning the back surface of the P+ single crystal silicon; d): selectively implanting H+ ions at the back surface repeatedly and then annealing to form N pillars in the P type region; and e): metallizing the back surface.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method for manufacturing vertical super junction drift layer of power semiconductor devices
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T21%3A52%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Gu,%20Hongming&rft.date=2018-08-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS10056452B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true