Static timing analysis with improved accuracy and efficiency

A method for performing static timing analysis of an integrated circuit design, wherein at least two timing paths share a shared node comprises propagating along the at least two timing paths a plurality of timing signals characterized by a set of timing parameters and determining respective values...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Belov, Anton, Moloney, Richard, Dadheech, Himanshu, Wrixon, Adrian, Keller, Maurice
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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