Die structures and methods of forming the same
Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor subs...
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creator | HONG, JIAN-WEI HSU, CHIA-HAO TING, KUOIANG YEH, SUNG-FENG |
description | Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via. |
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In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNBzyUxVKC4pKk0uKS1KLVZIzEtRyE0tychPKVbIT1NIyy_KzcxLVyjJAKpKzE3lYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxIeGeFqbGJhaWTk7GRCgBAJv_KnQ</recordid><startdate>20240821</startdate><enddate>20240821</enddate><creator>HONG, JIAN-WEI</creator><creator>HSU, CHIA-HAO</creator><creator>TING, KUOIANG</creator><creator>YEH, SUNG-FENG</creator><scope>EVB</scope></search><sort><creationdate>20240821</creationdate><title>Die structures and methods of forming the same</title><author>HONG, JIAN-WEI ; HSU, CHIA-HAO ; TING, KUOIANG ; YEH, SUNG-FENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI853489BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2024</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HONG, JIAN-WEI</creatorcontrib><creatorcontrib>HSU, CHIA-HAO</creatorcontrib><creatorcontrib>TING, KUOIANG</creatorcontrib><creatorcontrib>YEH, SUNG-FENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HONG, JIAN-WEI</au><au>HSU, CHIA-HAO</au><au>TING, KUOIANG</au><au>YEH, SUNG-FENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Die structures and methods of forming the same</title><date>2024-08-21</date><risdate>2024</risdate><abstract>Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Die structures and methods of forming the same |
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