TWI820648B

A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a g...

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Hauptverfasser:	YAMAMOTO, KOUKI, TAKATA, HARUHISA
Format:	Patent
Sprache:	chi
Schlagworte:	BASIC ELECTRIC ELEMENTS CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTINGELECTRIC POWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERATION SEMICONDUCTOR DEVICES SYSTEMS FOR STORING ELECTRIC ENERGY
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creator	YAMAMOTO, KOUKI TAKATA, HARUHISA
description	A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.
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subjects	BASIC ELECTRIC ELEMENTS CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTINGELECTRIC POWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERATION SEMICONDUCTOR DEVICES SYSTEMS FOR STORING ELECTRIC ENERGY
title	TWI820648B
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