Cool electron erasing in thin-film storage transistors

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltag...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHIEN, WU-YI HENRY, SAMACHISA, GEORGE, HARARI, ELI, SALAHUDDIN, SAYEEF
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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