Cool electron erasing in thin-film storage transistors

Cool electron erasing in thin-film storage transistors

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltag...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CHIEN, WU-YI HENRY, SAMACHISA, GEORGE, HARARI, ELI, SALAHUDDIN, SAYEEF
Format: Patent
Sprache:chi ; eng
Schlagworte:
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CHIEN, WU-YI HENRY
SAMACHISA, GEORGE
HARARI, ELI
SALAHUDDIN, SAYEEF
description A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI767512BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI767512BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI767512BB3</originalsourceid><addsrcrecordid>eNrjZDBzzs_PUUjNSU0uKcrPU0gtSizOzEtXyMxTKMnIzNNNy8zJVSguyS9KTE9VKClKzCvOBPGKeRhY0xJzilN5oTQ3g4Kba4izh25qQX58anFBYnJqXmpJfEi4p7mZuamhkZOTMRFKAGY4LfE</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Cool electron erasing in thin-film storage transistors</title><source>esp@cenet</source><creator>CHIEN, WU-YI HENRY ; SAMACHISA, GEORGE ; HARARI, ELI ; SALAHUDDIN, SAYEEF</creator><creatorcontrib>CHIEN, WU-YI HENRY ; SAMACHISA, GEORGE ; HARARI, ELI ; SALAHUDDIN, SAYEEF</creatorcontrib><description>A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.</description><language>chi ; eng</language><subject>ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220611&amp;DB=EPODOC&amp;CC=TW&amp;NR=I767512B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220611&amp;DB=EPODOC&amp;CC=TW&amp;NR=I767512B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHIEN, WU-YI HENRY</creatorcontrib><creatorcontrib>SAMACHISA, GEORGE</creatorcontrib><creatorcontrib>HARARI, ELI</creatorcontrib><creatorcontrib>SALAHUDDIN, SAYEEF</creatorcontrib><title>Cool electron erasing in thin-film storage transistors</title><description>A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.</description><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBzzs_PUUjNSU0uKcrPU0gtSizOzEtXyMxTKMnIzNNNy8zJVSguyS9KTE9VKClKzCvOBPGKeRhY0xJzilN5oTQ3g4Kba4izh25qQX58anFBYnJqXmpJfEi4p7mZuamhkZOTMRFKAGY4LfE</recordid><startdate>20220611</startdate><enddate>20220611</enddate><creator>CHIEN, WU-YI HENRY</creator><creator>SAMACHISA, GEORGE</creator><creator>HARARI, ELI</creator><creator>SALAHUDDIN, SAYEEF</creator><scope>EVB</scope></search><sort><creationdate>20220611</creationdate><title>Cool electron erasing in thin-film storage transistors</title><author>CHIEN, WU-YI HENRY ; SAMACHISA, GEORGE ; HARARI, ELI ; SALAHUDDIN, SAYEEF</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI767512BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2022</creationdate><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHIEN, WU-YI HENRY</creatorcontrib><creatorcontrib>SAMACHISA, GEORGE</creatorcontrib><creatorcontrib>HARARI, ELI</creatorcontrib><creatorcontrib>SALAHUDDIN, SAYEEF</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHIEN, WU-YI HENRY</au><au>SAMACHISA, GEORGE</au><au>HARARI, ELI</au><au>SALAHUDDIN, SAYEEF</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Cool electron erasing in thin-film storage transistors</title><date>2022-06-11</date><risdate>2022</risdate><abstract>A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_TWI767512BB
source esp@cenet
subjects ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
title Cool electron erasing in thin-film storage transistors
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T21%3A49%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHIEN,%20WU-YI%20HENRY&rft.date=2022-06-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETWI767512BB%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true