Structure and method of fabricating three-dimensional (3d) metal-insulator-metal (mim) capacitor and resistor in semi-additive plating metal wiring

Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to...

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Hauptverfasser: SEE, GUAN HUEI, TOH, CHIN HOCK, MORI, GLEN T, SUNDARRAJAN, ARVID
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creator SEE, GUAN HUEI
TOH, CHIN HOCK
MORI, GLEN T
SUNDARRAJAN, ARVID
description Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer; depositing a dielectric layer atop the first barrier layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI725062BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI725062BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI725062BB3</originalsourceid><addsrcrecordid>eNqNjbsKwkAQRdNYiPoPUybFgiSofUTR2oBlGHcnZmAfYXejH-IPm4cfYHU5l_tYJp9b9L2MvSdAq8BQbJ0C10CDD88SI9snxNYTCcWGbGBnUUNaqGwMoxZsQ68xOi8mhtSwyUBih5IHd5r1FDiMwBYCGRaoFEd-EXR6vpi7b_YDrJNFgzrQ5qerBM6n6ngR1LmawjBMlmJd3a-HfLfd52VZ_BH5AraDUAs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Structure and method of fabricating three-dimensional (3d) metal-insulator-metal (mim) capacitor and resistor in semi-additive plating metal wiring</title><source>esp@cenet</source><creator>SEE, GUAN HUEI ; TOH, CHIN HOCK ; MORI, GLEN T ; SUNDARRAJAN, ARVID</creator><creatorcontrib>SEE, GUAN HUEI ; TOH, CHIN HOCK ; MORI, GLEN T ; SUNDARRAJAN, ARVID</creatorcontrib><description>Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer; depositing a dielectric layer atop the first barrier layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210421&amp;DB=EPODOC&amp;CC=TW&amp;NR=I725062B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210421&amp;DB=EPODOC&amp;CC=TW&amp;NR=I725062B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SEE, GUAN HUEI</creatorcontrib><creatorcontrib>TOH, CHIN HOCK</creatorcontrib><creatorcontrib>MORI, GLEN T</creatorcontrib><creatorcontrib>SUNDARRAJAN, ARVID</creatorcontrib><title>Structure and method of fabricating three-dimensional (3d) metal-insulator-metal (mim) capacitor and resistor in semi-additive plating metal wiring</title><description>Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer; depositing a dielectric layer atop the first barrier layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjbsKwkAQRdNYiPoPUybFgiSofUTR2oBlGHcnZmAfYXejH-IPm4cfYHU5l_tYJp9b9L2MvSdAq8BQbJ0C10CDD88SI9snxNYTCcWGbGBnUUNaqGwMoxZsQ68xOi8mhtSwyUBih5IHd5r1FDiMwBYCGRaoFEd-EXR6vpi7b_YDrJNFgzrQ5qerBM6n6ngR1LmawjBMlmJd3a-HfLfd52VZ_BH5AraDUAs</recordid><startdate>20210421</startdate><enddate>20210421</enddate><creator>SEE, GUAN HUEI</creator><creator>TOH, CHIN HOCK</creator><creator>MORI, GLEN T</creator><creator>SUNDARRAJAN, ARVID</creator><scope>EVB</scope></search><sort><creationdate>20210421</creationdate><title>Structure and method of fabricating three-dimensional (3d) metal-insulator-metal (mim) capacitor and resistor in semi-additive plating metal wiring</title><author>SEE, GUAN HUEI ; TOH, CHIN HOCK ; MORI, GLEN T ; SUNDARRAJAN, ARVID</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI725062BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SEE, GUAN HUEI</creatorcontrib><creatorcontrib>TOH, CHIN HOCK</creatorcontrib><creatorcontrib>MORI, GLEN T</creatorcontrib><creatorcontrib>SUNDARRAJAN, ARVID</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SEE, GUAN HUEI</au><au>TOH, CHIN HOCK</au><au>MORI, GLEN T</au><au>SUNDARRAJAN, ARVID</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Structure and method of fabricating three-dimensional (3d) metal-insulator-metal (mim) capacitor and resistor in semi-additive plating metal wiring</title><date>2021-04-21</date><risdate>2021</risdate><abstract>Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer; depositing a dielectric layer atop the first barrier layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Structure and method of fabricating three-dimensional (3d) metal-insulator-metal (mim) capacitor and resistor in semi-additive plating metal wiring
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T07%3A59%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SEE,%20GUAN%20HUEI&rft.date=2021-04-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETWI725062BB%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true