MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF
The invention discloses a memory structure and a manufacturing method thereof. The memory structure includes a first transistor, a second transistor, a dielectric layer and a capacitor. The second transistor is located on one side of the first transistor. The dielectric layer covers the first transi...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | LEE, CHIH-PENG WEI, I-SHUAN LIN, JIA-YOU |
| description | The invention discloses a memory structure and a manufacturing method thereof. The memory structure includes a first transistor, a second transistor, a dielectric layer and a capacitor. The second transistor is located on one side of the first transistor. The dielectric layer covers the first transistor and the second transistor. The dielectric layer has a first opening and a second opening communicating with each other. The second opening is located at the side of the first opening. The capacitor is coupled between the first transistor and the second transistor. The capacitor includes a firstelectrode, a second electrode and an insulating layer. The first electrode is disposed on a surface of the first opening. The second electrode is disposed on the first electrode in the first openingand has an extension portion extending into the second opening. The extension portion covers the side surface of the first electrode exposed by the second opening. The insulating layer is disposed between the first electrode a |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI696266BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI696266BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI696266BB3</originalsourceid><addsrcrecordid>eNrjZDD0dfX1D4pUCA4JCnUOCQ1yVXD0c1HwdfQLdXME8T393BV8XUM8_F0UQjxcg1z93XgYWNMSc4pTeaE0N4OCm2uIs4duakF-fGpxQWJyal5qSXxIuKeZpZmRmZmTkzERSgA9DycH</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF</title><source>esp@cenet</source><creator>LEE, CHIH-PENG ; WEI, I-SHUAN ; LIN, JIA-YOU</creator><creatorcontrib>LEE, CHIH-PENG ; WEI, I-SHUAN ; LIN, JIA-YOU</creatorcontrib><description>The invention discloses a memory structure and a manufacturing method thereof. The memory structure includes a first transistor, a second transistor, a dielectric layer and a capacitor. The second transistor is located on one side of the first transistor. The dielectric layer covers the first transistor and the second transistor. The dielectric layer has a first opening and a second opening communicating with each other. The second opening is located at the side of the first opening. The capacitor is coupled between the first transistor and the second transistor. The capacitor includes a firstelectrode, a second electrode and an insulating layer. The first electrode is disposed on a surface of the first opening. The second electrode is disposed on the first electrode in the first openingand has an extension portion extending into the second opening. The extension portion covers the side surface of the first electrode exposed by the second opening. The insulating layer is disposed between the first electrode a</description><language>chi ; eng</language><subject>ELECTRICITY</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200611&DB=EPODOC&CC=TW&NR=I696266B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200611&DB=EPODOC&CC=TW&NR=I696266B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE, CHIH-PENG</creatorcontrib><creatorcontrib>WEI, I-SHUAN</creatorcontrib><creatorcontrib>LIN, JIA-YOU</creatorcontrib><title>MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF</title><description>The invention discloses a memory structure and a manufacturing method thereof. The memory structure includes a first transistor, a second transistor, a dielectric layer and a capacitor. The second transistor is located on one side of the first transistor. The dielectric layer covers the first transistor and the second transistor. The dielectric layer has a first opening and a second opening communicating with each other. The second opening is located at the side of the first opening. The capacitor is coupled between the first transistor and the second transistor. The capacitor includes a firstelectrode, a second electrode and an insulating layer. The first electrode is disposed on a surface of the first opening. The second electrode is disposed on the first electrode in the first openingand has an extension portion extending into the second opening. The extension portion covers the side surface of the first electrode exposed by the second opening. The insulating layer is disposed between the first electrode a</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD0dfX1D4pUCA4JCnUOCQ1yVXD0c1HwdfQLdXME8T393BV8XUM8_F0UQjxcg1z93XgYWNMSc4pTeaE0N4OCm2uIs4duakF-fGpxQWJyal5qSXxIuKeZpZmRmZmTkzERSgA9DycH</recordid><startdate>20200611</startdate><enddate>20200611</enddate><creator>LEE, CHIH-PENG</creator><creator>WEI, I-SHUAN</creator><creator>LIN, JIA-YOU</creator><scope>EVB</scope></search><sort><creationdate>20200611</creationdate><title>MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF</title><author>LEE, CHIH-PENG ; WEI, I-SHUAN ; LIN, JIA-YOU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI696266BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2020</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>LEE, CHIH-PENG</creatorcontrib><creatorcontrib>WEI, I-SHUAN</creatorcontrib><creatorcontrib>LIN, JIA-YOU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEE, CHIH-PENG</au><au>WEI, I-SHUAN</au><au>LIN, JIA-YOU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF</title><date>2020-06-11</date><risdate>2020</risdate><abstract>The invention discloses a memory structure and a manufacturing method thereof. The memory structure includes a first transistor, a second transistor, a dielectric layer and a capacitor. The second transistor is located on one side of the first transistor. The dielectric layer covers the first transistor and the second transistor. The dielectric layer has a first opening and a second opening communicating with each other. The second opening is located at the side of the first opening. The capacitor is coupled between the first transistor and the second transistor. The capacitor includes a firstelectrode, a second electrode and an insulating layer. The first electrode is disposed on a surface of the first opening. The second electrode is disposed on the first electrode in the first openingand has an extension portion extending into the second opening. The extension portion covers the side surface of the first electrode exposed by the second opening. The insulating layer is disposed between the first electrode a</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_TWI696266BB |
| source | esp@cenet |
| subjects | ELECTRICITY |
| title | MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-13T12%3A17%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LEE,%20CHIH-PENG&rft.date=2020-06-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETWI696266BB%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |