Mark structure for aligning layers of integrated circuit structure and methods of forming same

This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielect...

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Hauptverfasser:	CHEN, RUI, TANG, MING HAO, CHEN, ZHENG G, MORGENFELD, BRADLEY, REN, YUPING
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	CHEN, RUI TANG, MING HAO CHEN, ZHENG G MORGENFELD, BRADLEY REN, YUPING
description	This disclosure relates to a structure for aligning layers of an integrated circuit (IC) structure that may include a first dielectric layer positioned above a semiconductor substrate having one or more active devices, a trench stop layer positioned above the first dielectric layer, a second dielectric layer positioned above the trench stop layer, and a plurality of metal-filled marking trenches extending vertically through the second dielectric layer and the trench stop layer and at least partially into the first dielectric layer. The metal-filled trenches are electrically isolated from any active devices contained in the IC.
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language	chi ; eng
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	Mark structure for aligning layers of integrated circuit structure and methods of forming same
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