Method for forming semiconductor device for test and method for testing target transistors on front end of line-end-semiconductor device

According to example embodiments, a semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: WON, HYOSIG, HYUN, DAIJOON, JEONG, KWANGOK
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator WON, HYOSIG
HYUN, DAIJOON
JEONG, KWANGOK
description According to example embodiments, a semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TWI679435BB</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TWI679435BB</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TWI679435BB3</originalsourceid><addsrcrecordid>eNqNjb0KwkAQhNNYiPoO-wJXxR9sExQt7AKW4bjbiwfJbrhdfQYf24sINhYWwwzDfMy8eF5Qb-whcJo0ROpAcIiOyd-d5tbjIzp8DxRFwZKH4QtN3QSpTR0qaLIkUTIowAQhMSlgRjhAHwlNzubXwbKYBdsLrj6-KOB4aOqTwZFblNE6JNS2uZ63u_263FRV-cfkBZoRTPM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for forming semiconductor device for test and method for testing target transistors on front end of line-end-semiconductor device</title><source>esp@cenet</source><creator>WON, HYOSIG ; HYUN, DAIJOON ; JEONG, KWANGOK</creator><creatorcontrib>WON, HYOSIG ; HYUN, DAIJOON ; JEONG, KWANGOK</creatorcontrib><description>According to example embodiments, a semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.</description><language>chi ; eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191211&amp;DB=EPODOC&amp;CC=TW&amp;NR=I679435B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20191211&amp;DB=EPODOC&amp;CC=TW&amp;NR=I679435B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WON, HYOSIG</creatorcontrib><creatorcontrib>HYUN, DAIJOON</creatorcontrib><creatorcontrib>JEONG, KWANGOK</creatorcontrib><title>Method for forming semiconductor device for test and method for testing target transistors on front end of line-end-semiconductor device</title><description>According to example embodiments, a semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjb0KwkAQhNNYiPoO-wJXxR9sExQt7AKW4bjbiwfJbrhdfQYf24sINhYWwwzDfMy8eF5Qb-whcJo0ROpAcIiOyd-d5tbjIzp8DxRFwZKH4QtN3QSpTR0qaLIkUTIowAQhMSlgRjhAHwlNzubXwbKYBdsLrj6-KOB4aOqTwZFblNE6JNS2uZ63u_263FRV-cfkBZoRTPM</recordid><startdate>20191211</startdate><enddate>20191211</enddate><creator>WON, HYOSIG</creator><creator>HYUN, DAIJOON</creator><creator>JEONG, KWANGOK</creator><scope>EVB</scope></search><sort><creationdate>20191211</creationdate><title>Method for forming semiconductor device for test and method for testing target transistors on front end of line-end-semiconductor device</title><author>WON, HYOSIG ; HYUN, DAIJOON ; JEONG, KWANGOK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TWI679435BB3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2019</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>WON, HYOSIG</creatorcontrib><creatorcontrib>HYUN, DAIJOON</creatorcontrib><creatorcontrib>JEONG, KWANGOK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WON, HYOSIG</au><au>HYUN, DAIJOON</au><au>JEONG, KWANGOK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for forming semiconductor device for test and method for testing target transistors on front end of line-end-semiconductor device</title><date>2019-12-11</date><risdate>2019</risdate><abstract>According to example embodiments, a semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region, a first gate electrode and a second gate electrode on the PMOSFET region, a third gate electrode and a fourth gate electrode on the NMOSFET region, and a first contact and a second contact connected to the first gate electrode and the fourth gate electrode, respectively. The first to fourth gate cut electrodes define a gate cut region that passes between the first and third gate electrodes and between the second and fourth gate electrodes. A portion of each of the first and second contacts overlaps with the gate cut region when viewed from a plan view.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_TWI679435BB
source esp@cenet
subjects MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
title Method for forming semiconductor device for test and method for testing target transistors on front end of line-end-semiconductor device
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T00%3A05%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WON,%20HYOSIG&rft.date=2019-12-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETWI679435BB%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true