Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof
An electronics package includes a first dielectric substrate (34) having a first plurality of vias (50) formed through a thickness thereof, a metalized contact layer (48) coupled to a top surface (40) of the first dielectric substrate (34), and a first die (68) positioned within a first die opening...
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| creator | MCCONNELEE, PAUL ALAN GOWDA, ARUN VIRUPAKSHA |
| description | An electronics package includes a first dielectric substrate (34) having a first plurality of vias (50) formed through a thickness thereof, a metalized contact layer (48) coupled to a top surface (40) of the first dielectric substrate (34), and a first die (68) positioned within a first die opening (58) formed through the thickness of the first dielectric substrate (34). Metalized interconnects (56) are formed on a bottom surface (54) of the first dielectric substrate (34) and extend through the first plurality of vias (50) to contact the metalized contact layer (48). A second dielectric substrate (64) is coupled to the first dielectric substrate (34) and has a second plurality of vias (82) formed through a thickness thereof. Metalized interconnects (92) extend through the second plurality of vias (82) to contact the first plurality of metalized interconnects (56) and contact pads (49) of the first die (68). A first conductive element electrically (114) couples the first die (68) to the metalized contact laye |
| format | Patent |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Electrical interconnect structure for an embedded semiconductor device package and method of manufacturing thereof |
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