System and method for designing semiconductor package using computing system, apparatus for fabricating semiconductor package including the system, and semiconductor package designed by the method
A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of...
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| creator | JEONG, JAE-HOON LEE, WONOL HWANG, CHAN-SEOK CHEON, YOUNG-HOE HWANG, BO-SUN |
| description | A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters. |
| format | Patent |
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| language | chi ; eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | System and method for designing semiconductor package using computing system, apparatus for fabricating semiconductor package including the system, and semiconductor package designed by the method |
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