Method and apparatus for performing reduction operations on a set of vector elements

An apparatus and method are described for performing SIMD reduction operations. For example, one embodiment of a processor comprises: a value vector register containing a plurality of data element values to be reduced; an index vector register to store a plurality of index values indicating which va...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	HUGHES, CHRISTOPHER, KUNZMAN, DAVID M
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!