3d interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned d...

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Hauptverfasser:	MA, HANG-SHING, LEE, KEVIN J, SATTIRAJU, SESHU V, BOHR, MARK, KOTHARI, HITEN, YEOH, ANDREW W, PELTO, CHRISTOPHER M
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	MA, HANG-SHING LEE, KEVIN J SATTIRAJU, SESHU V BOHR, MARK KOTHARI, HITEN YEOH, ANDREW W PELTO, CHRISTOPHER M
description	A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	3d interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias
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